1. Field of the Invention
The present invention relates to a standard cell, a semiconductor integrated circuit device of standard cell scheme and a layout design method for a semiconductor integrated circuit device.
2. Description of the Related Art
A standard cell scheme is one of techniques for designing a large-scale integrated circuit (LSI). In the standard cell scheme, the desired circuit is constructed by preparing a plurality of sorts of small-scale circuits, called “standard cells”, in advance and then combining them. In a layout design for the LSI of the standard cell scheme, automatic arrangement and wiring which employ a software tool are performed. In the layout design of the automatic arrangement and wiring scheme, various circuits of different functions are constructed in a short time in such a way that the standard cells are arranged on a semiconductor substrate, and that the wiring among the standard cells is performed in accordance with specifications.
In the LSI based on the automatic arrangement and wiring in the prior art, wiring layers for wiring within the standard cells exists at lower layers, and wiring layers for the wiring among the standard cells is disposed at upper layers. Besides, in designing the LSI on the basis of the automatic arrangement and wiring, the standard cells are arranged so as to minimize a layout area, and the standard cells are thereafter interconnected using the upper wiring layers. Incidentally, there has been a standard cell which employs a dynamic circuit involving a precharge operation, not a static circuit, for the purposes of heightening an operating speed, reducing an area, and so forth (refer to, for example, P JP-A-2-121349 (U.S. Pat. No. 2,834,156)).
FIG. 5 is a circuit diagram showing the configuration of a 2-input AND circuit which is an example of the dynamic circuit. Referring to FIG. 5, letters A and B designate input signals, sign CLK designates a clock signal, and letter Q designates an output signal. Besides, reference numeral 101 (indicated by a thick line in the figure) designates a dynamic node. The dynamic node is a node whose potential falls into a floating state temporarily during an ordinary circuit operation, and which is susceptible to the potential variation of other wiring lines.
When the clock signal CLK is at a low level, a PMOS transistor (P1) is brought into an ON state, and the dynamic node 101 becomes a high level. This is called “precharge”. On this occasion, the output signal Q becomes the low level. When the clock signal changes to the high level, the 2-input AND circuit changes as explained below, depending upon the states of the input signals A and B.
First, when both the input signals A and B are at the high level, an NMOS transistor (N3) to which the clock signal CLK is fed and NMOS transistors (N1, N2) to which the input signals A and B are respectively fed are all brought into the ON states. The dynamic node 101 changes to the low level. Accordingly, the output signal Q changes to the high level. Besides, when at least one of the input signals A and B is at the high level, the dynamic node 101 is kept at the high level.
With the dynamic circuit which employs such precharge, a higher operating speed of the circuit can be attained, but the following problem occurs: When capacitive coupling exists between the dynamic node inside the circuit and the wiring lines in the vicinity thereof, the dynamic node has its potential changed under the influence of the potential variation of the wiring lines during the circuit operation, to incur the lowering of the operating margin of the circuit, in turn, the malfunction of the circuit.
In this regard, there has been a method wherein the dynamic node is covered with a power source wiring line, on which the wiring line between the standard cells can be laid (refer to, for example, P JP-A-2-121349 (U.S. Pat. No. 2,834,156)). Owing to this method, a shield is provided between the dynamic node and the overlying wiring line, so that the dynamic node is not influenced by the signal change of the overlying wiring line. There has also been a method wherein a wiring inhibition region is provided over the dynamic node, and the automatic wiring of the overlying wiring line is performed so as not to overlap the inhibition region (refer to, for example, JP-A-5-152290). Owing to this method, the capacitive coupling between the dynamic node and the overlying wiring line can be eliminated.
In the related art, it was sufficient to eliminate only the capacitive coupling between the wiring layer for the wiring lines within the standard cells and the overlying layer thereof, as stated in Patent Document 1 or 2. The reason therefor was that, since the standard cells themselves were constructed in consideration of the influence of the capacitive coupling, the wiring lines within the standard cells posed no problem, and that the wiring lines among the cells were laid only in the overlying layer of the wiring lines within the standard cells, as the result of the automatic arrangement and wiring, so the prevention of only the influence of the overlying layer was sufficient.
In recent years, however, there has been developed a circuit wherein a wiring layer which is capable of performing both the wiring within standard cells and the wiring among the standard cells is provided in order to reduce a circuit area. This circuit is formed by utilizing a wiring structure of three or more layers. More specifically, a wiring layer for the wiring within the standard cells is existent, the wiring layer for both the “wiring within the standard cells” and the “wiring among the standard cells” is existent on the first-mentioned wiring layer, and the second-mentioned wiring layer is overlaid with a wiring layer for the wiring among the standard cells.
Further, in recent years, with the microfabrication of a standard cell process, the coupling capacitance between wiring lines arranged in adjacency within a wiring layer of identical level (termed “side coupling capacitance”) has become more influential than the coupling capacitance between a certain wiring layer and the overlying layer (or underlying layer) thereof (termed “overlap capacitance”).
In the case where the wiring layer for both the wiring within the standard cells and the wiring among the standard cells is disposed under such a situation, the wiring line between the standard cells is sometimes laid in adjacency to a dynamic node, as the result of the automatic arrangement and wiring. In this case, the side coupling capacitance appears between the dynamic node and the adjacent wiring line between the standard cells, the potential variation of the wiring line between the standard cells is transmitted to the dynamic node through the side coupling capacitance, and the potential of the dynamic node might be inverted (that is, the malfunction of the circuit might be incurred).